CompSci 330, Computer Organization
assignment: chapter 4
Write out and hand in answers for the following exercises from the end of Chapter Four.
Some of the questions refer to this figure from the textbook, "COD Figure 4.17":
AND Rd, Rn, Rm
Interpretation: Reg[Rd]= Reg[Rn] AND Reg[Rm]
4.3
Consider the following instruction mix:
4.7
Problems in this exercise assume that logic blocks needed to implement a processor's datapath have the following latencies:
4.7.1
[20] <COD §4.4>
Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction.
Thus, the value of this control wire is available at the same time as the instruction.
Explain how we can extract this value directly from the instruction.
Hints: Carefully examine the opcodes shown in COD Figure 2.20 (LEGv8 instruction encoding).
Also, remember that LSR
and LSL
do not use the Rm field. Finally, ignore STXR
.
4.7.2 [5] <COD §4.4> What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)?
4.7.3
[10] <COD §4.4>
What is the latency of LDUR
?
(Check your answer carefully.
Many students place extra muxes on the critical path.)
4.7.4
[10] <COD §4.4>
What is the latency of STUR
?
(Check your answer carefully.
Many students place extra muxes on the critical path.)
4.7.5
[5] <COD §4.4>
What is the latency of CBZ
?
4.7.6
[5] <COD §4.4>
What is the latency of B
?
4.7.7 [5] <COD §4.4> What is the latency of an I-type instruction?
4.7.8 [5] <COD §4.4> What is the minimum clock period for this CPU?
4.16
In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:
Also, assume that instructions executed by the processor are broken down as follows:
4.16.1 [5] <COD §4.5> What is the clock cycle time in a pipelined and non-pipelined processor?
4.16.2
[10] <COD §4.5>
What is the total latency of an LDUR
instruction in a pipelined and non-pipelined processor?
4.16.3 [10] <COD §4.5> If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?
4.16.4 [10] <COD §4.5> Assuming there are no stalls or hazards, what is the utilization of the data memory? (i.e., what percentage of the instructions access data memory?)
4.16.5 [10] <COD §4.5> Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? (i.e., what percentage of the instructions write a value into the Register unit?)
LOOP: LDUR X10, [X1, #0] LDUR X11, [X1, #8] ADD X12, X10, X11 SUBI X1, X1, #16 CBNZ X12, LOOP
Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, that the pipeline has full forwarding support, and that branches are resolved in the EX (as opposed to the ID) stage.
SUBI
is in the IF stage.
End with the cycle during which the CBNZ
is in the IF stage.)