Solutions to homework asn2
SUB X9, X3, X4
LSL X9, X9, #3
ADD X11, X6, X9
LDUR X10, [X11, #0]
STUR X10, [X7, #64]
LSL X9, X0, #3
ADD X9, X6, X9
LSL X10, X1, #3
ADD X10, X7, X10
LDUR X0, [X9, #0]
ADDI X11, X9, #8
LDUR X9, [X11, #0]
ADD X9, X9, X0
STUR X9, [X10, #0]
LSL X9, X0, #3
ADD X9, X6, X9
LSL X10, X1, #3
ADD X10, X7, X10
LDUR X0, [X9, #0]
LDUR X9, [X9, #8]
ADD X9, X9, X0
STUR X9, [X10, #0]
LDR X9, [X6, X0, LSL #3]
ADD X10, X0, #1
LDR X11, [X6, X10, LSL #3]
ADD X12, X9, X11
STR X12, [X7, X1, LSL #3]
Little-Endian
+----+----+----+----+----+----+----+----+
| 12 | ef | cd | ab | | | | |
+----+----+----+----+----+----+----+----+
0 1 2 3 4 5 6 7
Big-Endian
+----+----+----+----+----+----+----+----+
| ab | cd | ef | 12 | | | | |
+----+----+----+----+----+----+----+----+
0 1 2 3 4 5 6 7
LSL X9, X3, #3
ADD X9, X6, X9
LDUR X9, [X9, #0]
LSL X10, X4, #3
ADD X10, X6, X10
LDUR X10, [X10, #0]
ADD X9, X9, X10
STUR X9, [X7, #64]
LDR X9, [X6, X3, LSL #3]
LDR X10, [X6, X4, LSL #3]
ADD X9, X9, X10
STUR X9, [X7, #64]
ADDI X9, X6, #8
ADD X10, X6, XZR
STUR X10, [X9, #0]
LDUR X9, [X9, #0]
ADD X0, X9, X10
0x5000000000000000
overflow
0xB000000000000000
no overflow
0xD000000000000000
overflow
ADD X0, X0, X0
SUB X17, X13, X15
(110 0101 1000) (01111) (000000) (01101) (10001)
1100 1011 0000 1111 0000 0001 1011 0001
0xcb0f01b1
LDUR X3, [X12, #4]
(111 1100 0010) (000000100) (00) (01100) (00011)
1111 1000 0100 0000 0100 0001 1000 0011
0xf8404183
The opcode would expand from 11 bits to 13.
Rm, Rn, and Rd would increase from 5 bits to 7 bits.
The opcode would expand from 10 bits to 12.
Rm and Rd would increase from 5 bits to 7 bits.
* Increasing the size of each bit field potentially makes each instruction
longer, potentially increasing the code size overall.
* However, increasing the number of registers could lead to less register
spillage, which would reduce the total number of instructions, possibly
reducing the code size overall.