Solutions to homework asn2

// 2.3
    SUB X9, X3, X4      // compute i-j
    LSL X9, X9, #3      // multiply by 8 to convert the word offset to a
    ADD X11, X6, X9     // compute &A[i-j]
    LDUR X10, [X11, #0] // load A[i-j]
    STUR X10, [X7, #64] // store in B[8]


// 2.4
//  B[g] = A[f] + A[f+1]
    LSL X9, X0, #3      // X9 = f*8
    ADD X9, X6, X9      // X9 = &A[f]
    LSL X10, X1, #3     // X10 = g*8
    ADD X10, X7, X10    // X10 = &B[g]
    LDUR X0, [X9, #0]   // f = A[f]
    ADDI X11, X9, #8    // (*) X11 = X9 + 8 (i.e., X11 = &A[f+1])
    LDUR X9, [X11, #0]  // X9 = A[f+1]
    ADD X9, X9, X0      // X9 = X9 + f (i.e., x9 = A[f+1] + A[f])
    STUR X9, [X10, #0]  // B[g] = X9 (i.e., B[g] = A[f+1] + A[f])


// 2.5
// Using LEGv8
    LSL X9, X0, #3      // X9 = f*8
    ADD X9, X6, X9      // X9 = &A[f]
    LSL X10, X1, #3     // X10 = g*8
    ADD X10, X7, X10    // X10 = &B[g]
    LDUR X0, [X9, #0]   // f = A[f]
    LDUR X9, [X9, #8]   // X9 = A[f+1]
    ADD X9, X9, X0      // X9 = X9 + f (i.e., X9 = A[f+1] + A[f])
    STUR X9, [X10, #0]  // B[g] = X9 (i.e., B[g] = A[f+1] + A[f])

// Using ARMv8
    LDR X9, [X6, X0, LSL #3]    // f = A[f]
    ADD X10, X0, #1             // X10 = f+1
    LDR X11, [X6, X10, LSL #3]  // x11 = A[f+1]
    ADD X12, X9, X11            // X12 = A[f] + A[f+1]
    STR X12, [X7, X1, LSL #3]   // B[g] = X12


// 2.6  Show how the value 0xabcdef12 would be arranged in memory
        Little-Endian
            +----+----+----+----+----+----+----+----+
            | 12 | ef | cd | ab |    |    |    |    |
            +----+----+----+----+----+----+----+----+
                0    1    2    3    4    5    6    7

        Big-Endian
            +----+----+----+----+----+----+----+----+
            | ab | cd | ef | 12 |    |    |    |    |
            +----+----+----+----+----+----+----+----+
                0    1    2    3    4    5    6    7


// 2.8
// Using LEGv8
// X9 = A[i]
    LSL X9, X3, #3
    ADD X9, X6, X9
    LDUR X9, [X9, #0]
    // X10 = A[j]
    LSL X10, X4, #3
    ADD X10, X6, X10
    LDUR X10, [X10, #0]
    ADD X9, X9, X10             // compute A[i] + A[j]   
    STUR X9, [X7, #64]          // store the result in B[8] // Using ARMv8
    LDR X9, [X6, X3, LSL #3]    // X9 = A[i]
    LDR X10, [X6, X4, LSL #3]   // X10 = A[j]
    ADD X9, X9, X10             // X9 = X9 + X10
    STUR X9, [X7, #64]          // B[8] = X9


// 2.9          f = 2 * (&A)
//  x0  x1      x2      x3      x4      x6      x7
//  f   g       h       i       j       &a      &b

    ADDI X9, X6, #8     // x9 <- &(a+1)
    ADD X10, X6, XZR    // x10 <- &a
    STUR X10, [X9, #0]  // mem[a+1] <- &a
    LDUR X9, [X9, #0]   // x9 <- mem[a+1]
    ADD X0, X9, X10     // x0 <- &a + &a

// Note: This is not efficiently written code!


// 2.11
// 2.11.1
     0x5000000000000000
// 2.11.2
     overflow
// 2.11.3
     0xB000000000000000
// 2.11.4
     no overflow
// 2.11.5
     0xD000000000000000
// 2.11.6
     overflow


// 2.13
//  R-type:
    ADD X0, X0, X0


// 2.15
//  R-type
    SUB X17, X13, X15
        (110 0101 1000)  (01111)  (000000)  (01101)  (10001)
        1100 1011 0000 1111 0000 0001 1011 0001
        0xcb0f01b1


// 2.16
// D-type
    LDUR X3, [X12, #4]
        (111 1100 0010)  (000000100)  (00)  (01100)  (00011)
        1111 1000 0100 0000 0100 0001 1000 0011
        0xf8404183


// 2.17
// 2.17.1
    The opcode would expand from 11 bits to 13.
    Rm, Rn, and Rd would increase from 5 bits to 7 bits.
// 2.17.2
    The opcode would expand from 10 bits to 12.
    Rm and Rd would increase from 5 bits to 7 bits.
// 2.17.3
    * Increasing the size of each bit field potentially makes each instruction
    longer, potentially increasing the code size overall.
    * However, increasing the number of registers could lead to less register
    spillage, which would reduce the total number of instructions, possibly
    reducing the code size overall.